Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%.”įind the technical paper here. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. “This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. A technical paper titled “A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers” was published by researchers at Università degli Studi di Catania, Italy.
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